40 citations · 240 across the 22 of their papers we have counts for
15 papers · 1 filter
CorrectNet: Robustness Enhancement of Analog In-Memory Computing for Neural Networks by Error Suppression and Compensation
Amro Eldebiky, Grace Li Zhang, Georg Boecherer +2
The last decade has witnessed the breakthrough of deep neural networks (DNNs) in many fields. With the increasing depth of DNNs, hundreds of millions of multiply-and-accumulate (MA…
VirtualSync+: Timing Optimization with Virtual Synchronization
Grace Li Zhang, Bing Li, Xing Huang +4
In digital circuit designs, sequential components such as flip-flops are used to synchronize signal propagations. Logic computations are aligned at and thus isolated by flip-flop s…
Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning
Li Zhang, Bing Li, Jinglan Liu +2
At submicron manufacturing technology nodes, pro- cess variations affect circuit performance significantly. To counter these variations, engineers are reserving more timing margin…
PieceTimer: A Holistic Timing Analysis Framework Considering Setup/Hold Time Interdependency Using A Piecewise Model
Grace Li Zhang, Bing Li, Ulf Schlichtmann
In static timing analysis, clock-to-q delays of flip-flops are considered as constants. Setup times and hold times are characterized separately and also used as constants. The char…
EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers
Grace Li Zhang, Bing Li, Ulf Schlichtmann
At nanometer manufacturing technology nodes, process variations significantly affect circuit performance. To combat them, post- silicon clock tuning buffers can be deployed to bala…
Sampling-based Buffer Insertion for Post-Silicon Yield Improvement under Process Variability
Grace Li Zhang, Bing Li, Ulf Schlichtmann
At submicron manufacturing technology nodes process variations affect circuit performance significantly. This trend leads to a large timing margin and thus overdesign to maintain y…