activity
20172020
most citedSparse Matrix Multiplication on CAM Based Accelerator

11 citations · 18 across the 8 of their papers we have counts for

collaborators

10 papers

cs.AR2020

WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders

Leonid Yavits, Lois Orosa, Suyash Mahar +4

Resistive memories have limited lifetime caused by limited write endurance and highly non-uniform write access patterns. Two main techniques to mitigate endurance-related memory fa…

cs.ET20194 cited

BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data

Roman Kaplan, Leonid Yavits, Ran Ginosar

Genome sequences contain hundreds of millions of DNA base pairs. Finding the degree of similarity between two genomes requires executing a compute-intensive dynamic programming alg…

cs.DC20181 cited

AIDA: Associative DNN Inference Accelerator

Leonid Yavits, Roman Kaplan, Ran Ginosar

We propose AIDA, an inference engine for accelerating fully-connected (FC) layers of Deep Neural Network (DNN). AIDA is an associative in-memory processor, where the bulk of data n…

q-bio.GN2018

RASSA: Resistive Pre-Alignment Accelerator for Approximate DNA Long Read Mapping

Roman Kaplan, Leonid Yavits, Ran Ginosar

DNA read mapping is a computationally expensive bioinformatics task, required for genome assembly and consensus polishing. It requires to find the best-fitting location for each DN…

cs.AR2018

PRINS: Resistive CAM Processing in Storage

Leonid Yavits, Roman Kaplan, Ran Ginosar

Near-data in-storage processing research has been gaining momentum in recent years. Typical processing-in-storage architecture places a single or several processing cores inside th…

cs.AR201711 cited

Sparse Matrix Multiplication on CAM Based Accelerator

Leonid Yavits, Ran Ginosar

Sparse matrix multiplication is an important component of linear algebra computations. In this paper, an architecture based on Content Addressable Memory (CAM) and Resistive Conten…