82 citations · 125 across the 17 of their papers we have counts for
17 papers
A Journey in Shared Memory Land
Ran Ginosar
I have greatly enjoyed spending many years in studying parallel computing. My journey goes thorough MP-C, PLURAL, Async Plural, HAL, RC64 and more. As a PhD student at Princeton I…
WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders
Leonid Yavits, Lois Orosa, Suyash Mahar +4
Resistive memories have limited lifetime caused by limited write endurance and highly non-uniform write access patterns. Two main techniques to mitigate endurance-related memory fa…
BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data
Roman Kaplan, Leonid Yavits, Ran Ginosar
Genome sequences contain hundreds of millions of DNA base pairs. Finding the degree of similarity between two genomes requires executing a compute-intensive dynamic programming alg…
AIDA: Associative DNN Inference Accelerator
Leonid Yavits, Roman Kaplan, Ran Ginosar
We propose AIDA, an inference engine for accelerating fully-connected (FC) layers of Deep Neural Network (DNN). AIDA is an associative in-memory processor, where the bulk of data n…
RASSA: Resistive Pre-Alignment Accelerator for Approximate DNA Long Read Mapping
Roman Kaplan, Leonid Yavits, Ran Ginosar
DNA read mapping is a computationally expensive bioinformatics task, required for genome assembly and consensus polishing. It requires to find the best-fitting location for each DN…
PRINS: Resistive CAM Processing in Storage
Leonid Yavits, Roman Kaplan, Ran Ginosar
Near-data in-storage processing research has been gaining momentum in recent years. Typical processing-in-storage architecture places a single or several processing cores inside th…
Sparse Matrix Multiplication on CAM Based Accelerator
Leonid Yavits, Ran Ginosar
Sparse matrix multiplication is an important component of linear algebra computations. In this paper, an architecture based on Content Addressable Memory (CAM) and Resistive Conten…
Sparse Matrix Multiplication On An Associative Processor
L. Yavits, A. Morad, R. Ginosar
Sparse matrix multiplication is an important component of linear algebra computations. Implementing sparse matrix multiplication on an associative processor (AP) enables high level…
Cache Hierarchy Optimization
Leonid Yavits, Amir Morad, Ran Ginosar
Power consumption, off-chip memory bandwidth, chip area and Network on Chip (NoC) capacity are among main chip resources limiting the scalability of Chip Multiprocessors (CMP). A c…
The Effect of Temperature on Amdahl Law in 3D Multicore Era
Leonid Yavits, Amir Morad, Ran Ginosar
This work studies the influence of temperature on performance and scalability of 3D Chip Multiprocessors (CMP) from Amdahl law perspective. We find that 3D CMP may reach its therma…
MultiAmdahl: Optimal Resource Allocation in Heterogeneous Architectures
Leonid Yavits, Amir Morad, Uri Weiser +1
Future multiprocessor chips will integrate many different units, each tailored to a specific computation. When designing such a system, the chip architect must decide how to distri…
A Resistive CAM Processing-in-Storage Architecture for DNA Sequence Alignment
Roman Kaplan, Leonid Yavits, Ran Ginosar +1
A novel processing-in-storage (PRinS) architecture based on Resistive CAM (ReCAM) is described and proposed for Smith-Waterman (S-W) sequence alignment. The ReCAM massively-paralle…
Effect of Data Sharing on Private Cache Design in Chip Multiprocessors
Leonid Yavits, Amir Morad, Ran Ginosar
In multithreaded applications with high degree of data sharing, the miss rate of private cache is shown to exhibit a compulsory miss component. It manifests because at least some o…
Convex Optimization of Real Time SoC
L. Yavits, A. Morad, R. Ginosar +1
Convex optimization methods are employed to optimize a real-time (RT) system-on-chip (SoC) under a variety of physical resource-driven constraints, demonstrated on an industry MPEG…
Thermal analysis of 3D associative processor
Leonid Yavits, Amir Morad, Ran Ginosar
Thermal density and hot spots limit three-dimensional (3D) implementation of massively-parallel SIMD processors and prohibit stacking DRAM dies above them. This study proposes repl…
The Effect of Communication and Synchronization on Amdahl Law in Multicore Systems
Leonid Yavits, Amir Morad, Ran Ginosar
This work analyses the effects of sequential-to-parallel synchronization and inter-core communication on multicore performance, speedup and scaling. A modification of Amdahl law is…
Computer Architecture with Associative Processor Replacing Last Level Cache and SIMD Accelerator
Leonid Yavits, Amir Morad, Ran Ginosar
This study presents a novel computer architecture where a last level cache and a SIMD accelerator are replaced by an Associative Processor. Associative Processor combines data stor…