82 citations · 193 across the 24 of their papers we have counts for
13 papers · 1 filter
PiC-BNN: A 128-kbit 65 nm Processing-in-CAM-Based End-to-End Binary Neural Network Accelerator
Yuval Harary, Almog Sharoni, Esteban Garzón +3
Binary Neural Networks (BNNs), where weights and activations are constrained to binary values (+1, -1), are a highly efficient alternative to traditional neural networks. Unfortuna…
DRAMA: Commodity DRAM based Content Addressable Memory
Leonid Yavits
Fast parallel search capabilities on large datasets provided by content addressable memories (CAM) are required across multiple application domains. However compared to RAM, CAMs f…
Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for Approximate Matching Applications
Esteban Garzón, Roman Golman, Zuher Jahshan +5
We propose a novel Hamming distance tolerant content-addressable memory (HD-CAM) for energy-efficient in memory approximate matching applications. HD-CAM implements approximate sea…
WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders
Leonid Yavits, Lois Orosa, Suyash Mahar +4
Resistive memories have limited lifetime caused by limited write endurance and highly non-uniform write access patterns. Two main techniques to mitigate endurance-related memory fa…
PRINS: Resistive CAM Processing in Storage
Leonid Yavits, Roman Kaplan, Ran Ginosar
Near-data in-storage processing research has been gaining momentum in recent years. Typical processing-in-storage architecture places a single or several processing cores inside th…
Sparse Matrix Multiplication on CAM Based Accelerator
Leonid Yavits, Ran Ginosar
Sparse matrix multiplication is an important component of linear algebra computations. In this paper, an architecture based on Content Addressable Memory (CAM) and Resistive Conten…
Cache Hierarchy Optimization
Leonid Yavits, Amir Morad, Ran Ginosar
Power consumption, off-chip memory bandwidth, chip area and Network on Chip (NoC) capacity are among main chip resources limiting the scalability of Chip Multiprocessors (CMP). A c…
The Effect of Temperature on Amdahl Law in 3D Multicore Era
Leonid Yavits, Amir Morad, Ran Ginosar
This work studies the influence of temperature on performance and scalability of 3D Chip Multiprocessors (CMP) from Amdahl law perspective. We find that 3D CMP may reach its therma…
MultiAmdahl: Optimal Resource Allocation in Heterogeneous Architectures
Leonid Yavits, Amir Morad, Uri Weiser +1
Future multiprocessor chips will integrate many different units, each tailored to a specific computation. When designing such a system, the chip architect must decide how to distri…
Effect of Data Sharing on Private Cache Design in Chip Multiprocessors
Leonid Yavits, Amir Morad, Ran Ginosar
In multithreaded applications with high degree of data sharing, the miss rate of private cache is shown to exhibit a compulsory miss component. It manifests because at least some o…
Thermal analysis of 3D associative processor
Leonid Yavits, Amir Morad, Ran Ginosar
Thermal density and hot spots limit three-dimensional (3D) implementation of massively-parallel SIMD processors and prohibit stacking DRAM dies above them. This study proposes repl…
The Effect of Communication and Synchronization on Amdahl Law in Multicore Systems
Leonid Yavits, Amir Morad, Ran Ginosar
This work analyses the effects of sequential-to-parallel synchronization and inter-core communication on multicore performance, speedup and scaling. A modification of Amdahl law is…
Computer Architecture with Associative Processor Replacing Last Level Cache and SIMD Accelerator
Leonid Yavits, Amir Morad, Ran Ginosar
This study presents a novel computer architecture where a last level cache and a SIMD accelerator are replaced by an Associative Processor. Associative Processor combines data stor…