133 citations · 473 across the 24 of their papers we have counts for
6 papers · 1 filter
Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators
Weiwen Jiang, Qiuwen Lou, Zheyu Yan +4
Co-exploration of neural architectures and hardware design is promising to simultaneously optimize network accuracy and hardware efficiency. However, state-of-the-art neural archit…
Nonvolatile Spintronic Memory Cells for Neural Networks
Andrew W. Stephan, Qiuwen Lou, Michael Niemier +2
A new spintronic nonvolatile memory cell analogous to 1T DRAM with non-destructive read is proposed. The cells can be used as neural computing units. A dual-circuit neural network…
Application-level Studies of Cellular Neural Network-based Hardware Accelerators
Qiuwen Lou, Indranil Palit, Tang Li +3
As cost and performance benefits associated with Moore's Law scaling slow, researchers are studying alternative architectures (e.g., based on analog and/or spiking circuits) and/or…
Fully Distributed Packet Scheduling Framework for Handling Disturbances in Lossy Real-Time Wireless Networks
Tianyu Zhang, Tao Gong, Song Han +2
Along with the rapid growth of Industrial Internet-of-Things (IIoT) applications and their penetration into many industry sectors, real-time wireless networks (RTWNs) have been pla…
Eva-CiM: A System-Level Performance and Energy Evaluation Framework for Computing-in-Memory Architectures
Di Gao, Dayane Reis, Xiaobo Sharon Hu +1
Computing-in-Memory (CiM) architectures aim to reduce costly data transfers by performing arithmetic and logic operations in memory and hence relieve the pressure due to the memory…
CC-Net: Image Complexity Guided Network Compression for Biomedical Image Segmentation
Suraj Mishra, Peixian Liang, Adam Czajka +2
Convolutional neural networks (CNNs) for biomedical image analysis are often of very large size, resulting in high memory requirement and high latency of operations. Searching for…