124 citations · 388 across the 53 of their papers we have counts for
35 papers · 1 filter
Terracotta: Enabling the Adoption of New DRAM Techniques via a Flexible DRAM Interface and Memory Controller
Harsh Songara, Konstantinos Kanellopoulos, F. Nisa Bostancı +6
DRAM continues to limit the performance, energy efficiency, and robustness of modern systems. Many prior works propose DRAM techniques that support in-DRAM computation, improve mem…
CertiFlash: A Formal Verification Framework for Flash Translation Layers in Computational Solid State Drives
Harshita Gupta, Mayank Kabra, Rakesh Nadig +10
Data-intensive applications move large amounts of data from storage to the compute unit, incurring significant data movement overhead. Storage-centric computing reduces this overhe…
Clutch: High Performance Vector-Scalar Comparison using DRAM via Chunked Temporal Coding
Daichi Tokuda, Tatsuya Kubo, Ismail Emir Yuksel +8
Vector-scalar comparison is a fundamental computation primitive that compares each element in a vector against a single scalar value. It is widely used in various data-intensive wo…
DejaVu: Why You Should Write to Your DRAM Rows Twice, Carefully
Haocong Luo, İsmail Emir Yüksel, Ataberk Olgun +4
We provide the first experimental demonstration of DejaVu, a phenomenon where the data previously written to DRAM cells affects DRAM's vulnerability to read disturbance. Our experi…
PuDGhost: Experimental Analysis of Computation Result Corruption in Processing-using-DRAM Operations on Real DRAM Chips and Implications for Future Systems
Daichi Tokuda, İsmail Emir Yüksel, Tatsuya Kubo +7
Processing-using-DRAM (PuD) is a promising computation paradigm that alleviates frequent data movement between main memory and processing units by using each DRAM column as a compu…
A Modern Large-Scale Memory Characterization Laboratory
Ataberk Olgun, Haocong Luo, Ismail Emir Yuksel +3
Real memory chip characterization yields insights into fundamental operational characteristics of modern memory, enabling new mechanisms that improve memory performance, robustness…
DiscoRD: An Experimental Methodology for Quickly Discovering the Reliable Read Disturbance Threshold of Real DRAM Chips
Ataberk Olgun, F. Nisa Bostanci, Ismail Emir Yuksel +4
State-of-the-art DRAM read disturbance mitigations rely on the read disturbance threshold (RDT) (e.g., the number of aggressor row activations needed to induce the first read distu…
In-DRAM True Random Number Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Real DRAM Chips
Ismail Emir Yuksel, Ataberk Olgun, F. Nisa Bostanci +5
In this work, we experimentally demonstrate that it is possible to generate true random numbers at high throughput and low latency in commercial off-the-shelf (COTS) DRAM chips by…
ColumnDisturb: Understanding Column-based Read Disturbance in Real DRAM Chips and Implications for Future Systems
İsmail Emir Yüksel, Ataberk Olgun, F. Nisa Bostancı +3
We experimentally demonstrate a new widespread read disturbance phenomenon, ColumnDisturb, in real commodity DRAM chips. By repeatedly opening or keeping a DRAM row (aggressor row)…
Cleaning up the Mess: Re-Evaluating the Real-System Modeling Accuracy of Ramulator 2.0
F. Nisa Bostanci, Haocong Luo, Ataberk Olgun +4
A MICRO 2024 best paper runner-up publication (the Mess paper) with all three artifact badges awarded (including ``Reproducible'') proposes a new benchmark to evaluate real and sim…
Variable Read Disturbance: An Experimental Analysis of Temporal Variation in DRAM Read Disturbance
Ataberk Olgun, F. Nisa Bostanci, Ismail Emir Yuksel +6
Modern DRAM chips are subject to read disturbance errors. State-of-the-art read disturbance mitigations rely on accurate and exhaustive characterization of the read disturbance thr…
Understanding RowHammer Under Reduced Refresh Latency: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions
Yahya Can Tuğrul, A. Giray Yağlıkçı, İsmail Emir Yüksel +6
RowHammer is a major read disturbance mechanism in DRAM where repeatedly accessing (hammering) a row of DRAM cells (DRAM row) induces bitflips in physically nearby DRAM rows (victi…
An Experimental Characterization of Combined RowHammer and RowPress Read Disturbance in Modern DRAM Chips
Haocong Luo, Ismail Emir Yüksel, Ataberk Olgun +3
DRAM read disturbance can break memory isolation, a fundamental property to ensure system robustness (i.e., reliability, security, safety). RowHammer and RowPress are two different…
RowPress Vulnerability in Modern DRAM Chips
Haocong Luo, Ataberk Olgun, A. Giray Yağlıkçı +6
Memory isolation is a critical property for system reliability, security, and safety. We demonstrate RowPress, a DRAM read disturbance phenomenon different from the well-known RowH…
Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis
Ismail Emir Yuksel, Yahya Can Tugrul, F. Nisa Bostanci +8
We experimentally analyze the computational capability of commercial off-the-shelf (COTS) DRAM chips and the robustness of these capabilities under various timing delays between DR…
MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Processing
Geraldo F. Oliveira, Ataberk Olgun, Abdullah Giray Yağlıkçı +4
Processing-using-DRAM (PUD) is a processing-in-memory (PIM) approach that uses a DRAM array's massive internal parallelism to execute very-wide data-parallel operations, in a singl…
Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis
Ismail Emir Yuksel, Yahya Can Tugrul, Ataberk Olgun +7
Processing-using-DRAM (PuD) is an emerging paradigm that leverages the analog operational properties of DRAM circuitry to enable massively parallel in-DRAM computation. PuD has the…
PULSAR: Simultaneous Many-Row Activation for Reliable and High-Performance Computing in Off-the-Shelf DRAM Chips
Ismail Emir Yuksel, Yahya Can Tugrul, F. Nisa Bostanci +8
Data movement between the processor and the main memory is a first-order obstacle against improving performance and energy efficiency in modern systems. To address this obstacle, P…
DaPPA: A Unified Data-Parallel Programming Framework for Efficient Processing-in-Memory Execution
Geraldo F. Oliveira, Alain Kohli, David Novo +5
Processing-in-memory (PIM) alleviates data-movement bottlenecks by placing computation near or inside memory. Two general-purpose PIM paradigms are now practical: processing-near-m…
Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator
Haocong Luo, Yahya Can Tuğrul, F. Nisa Bostancı +3
We present Ramulator 2.0, a highly modular and extensible DRAM simulator that enables rapid and agile implementation and evaluation of design changes in the memory controller and D…
TuRaN: True Random Number Generation Using Supply Voltage Underscaling in SRAMs
İsmail Emir Yüksel, Ataberk Olgun, Behzad Salami +6
Prior works propose SRAM-based TRNGs that extract entropy from SRAM arrays. SRAM arrays are widely used in a majority of specialized or general-purpose chips that perform the compu…
DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips
Ataberk Olgun, Hasan Hassan, A. Giray Yağlıkçı +6
To understand and improve DRAM performance, reliability, security and energy efficiency, prior works study characteristics of commodity DRAM chips. Unfortunately, state-of-the-art…
HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips
Abdullah Giray Yağlıkçı, Ataberk Olgun, Minesh Patel +5
DRAM is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent data loss. Refresh operations degrade system performance by interferi…
Self-Managing DRAM: A Low-Cost Framework for Enabling Autonomous and Efficient in-DRAM Operations
Hasan Hassan, Ataberk Olgun, A. Giray Yaglikci +2
The memory controller is in charge of managing DRAM maintenance operations (e.g., refresh, RowHammer protection, memory scrubbing) to reliably operate modern DRAM chips. Implementi…