73 citations · 123 across the 16 of their papers we have counts for
17 papers · 1 filter
Variable Read Disturbance: An Experimental Analysis of Temporal Variation in DRAM Read Disturbance
Ataberk Olgun, F. Nisa Bostanci, Ismail Emir Yuksel +6
Modern DRAM chips are subject to read disturbance errors. State-of-the-art read disturbance mitigations rely on accurate and exhaustive characterization of the read disturbance thr…
Rethinking the Producer-Consumer Relationship in Modern DRAM-Based Systems
Minesh Patel, Taha Shahroodi, Aditya Manglik +4
Generational improvements to commodity DRAM throughout half a century have long solidified its prevalence as main memory across the computing industry. However, overcoming today's…
NEON: Enabling Efficient Support for Nonlinear Operations in Resistive RAM-based Neural Network Accelerators
Aditya Manglik, Minesh Patel, Haiyu Mao +4
Resistive Random-Access Memory (RRAM) is well-suited to accelerate neural network (NN) workloads as RRAM-based Processing-in-Memory (PIM) architectures natively support highly-para…
HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips
Abdullah Giray Yağlıkçı, Ataberk Olgun, Minesh Patel +5
DRAM is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent data loss. Refresh operations degrade system performance by interferi…
Enabling Effective Error Mitigation in Memory Chips That Use On-Die Error-Correcting Codes
Minesh Patel
Improvements in main memory storage density are primarily driven by process technology scaling, which negatively impacts reliability by exacerbating various circuit-level error mec…
A Case for Transparent Reliability in DRAM Systems
Minesh Patel, Taha Shahroodi, Aditya Manglik +4
Today's systems have diverse needs that are difficult to address using one-size-fits-all commodity DRAM. Unfortunately, although system designers can theoretically adapt commodity…