6 citations · 6 across the 3 of their papers we have counts for
3 papers
cs.ET2017
Neutron-induced strike: Study of multiple node charge collection in 14nm FinFETs
Nanditha P. Rao, Madhav P. Desai
FinFETs have replaced the conventional bulk CMOS transistors in the sub-20nm technology. One of the key issues to consider is, the vulnerability of FinFET based circuits to multipl…
cs.AR2016
Neutron induced strike: On the likelihood of multiple bit-flips in logic circuits
Nanditha P. Rao, Madhav P. Desai
High energy particles from cosmic rays or packaging materials can generate a glitch or a current transient (single event transient or SET) in a logic circuit. This SET can eventual…
cs.AR2014★ 6 cited
On the likelihood of multiple bit upsets in logic circuits
Nanditha P. Rao, Shahbaz Sarik, Madhav P. Desai
Soft errors have a significant impact on the circuit reliability at nanoscale technologies. At the architectural level, soft errors are commonly modeled by a probabilistic bit-flip…