3 papers
cs.AR2026
BRIM: Workload-Balanced Dual-Sided Bit-Serial Sparse Inference Accelerator
Varun Manjunath, Ruokai Yin, Donghyun Lee +2
Bit-serial accelerators exploit bit-level sparsity to reduce DNN inference cost, but existing designs exploit sparsity on only one operand, bounding the speedup. Extending sparsity…
cs.AR2025
DiffAxE: Diffusion-driven Hardware Accelerator Generation and Design Space Exploration
Arkapravo Ghosh, Abhishek Moitra, Abhiroop Bhattacharjee +2
Design space exploration (DSE) is critical for developing optimized hardware architectures, especially for AI workloads such as deep neural networks (DNNs) and large language model…
cs.AR2025
MEADOW: Memory-efficient Dataflow and Data Packing for Low Power Edge LLMs
Abhishek Moitra, Arkapravo Ghosh, Shrey Agarwal +3
The computational and memory challenges of large language models (LLMs) have sparked several optimization approaches towards their efficient implementation. While prior LLM-targete…