2 papers
cs.AR2026
A Progressive Approach to Synthesizable RTL Design Generation Using LLMs
Xiangfei Kong, Tasnim Tabassum, Marwan Abdelwahab +1
Large language models can generate register-transfer-level (RTL) designs directly from natural language specifications. Their failures, however, arise mostly from understanding rat…
cs.AR2026
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs
Sazzadul Islam, Tasnim Tabassum, Hao Zheng
Generating synthesizable Verilog for large, hierarchical hardware designs remains a significant challenge for large language models (LLMs), which struggle to replicate the structur…