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cs.AR2026
A Switch-Centric In-Network Architecture for Accelerating LLM Inference in Shared-Memory Network
Aojie Jiang, Kang Zhu, Zhiheng Zhang +4
Tensor parallelism (TP) has become a key technique for latency-sensitive LLM inference, but it introduces frequent, tightly synchronized All-Reduce operations that lie directly on…
cs.AR2021
Memory-Efficient CNN Accelerator Based on Interlayer Feature Map Compression
Zhuang Shao, Xiaoliang Chen, Li Du +6
Existing deep convolutional neural networks (CNNs) generate massive interlayer feature data during network inference. To maintain real-time processing in embedded systems, large on…