Ta-based S-I-S junctions for integrated superconducting electronics

Abstract

In this work, we have presented S-I-S Josephson junctions with $\alpha$-Ta electrodes and a ${\mathrm{TaO}}_x$ barrier. We grew base and top $\alpha$-Ta electrodes using seed layer engineering, showing both Nb and ${\mathrm{TaN}}_x$ are viable seed layer choices, and particularly emphasize that at room temperature a re-seed layer is required to nucleate $\alpha$-Ta for the top electrode. However, we note that the choice of seed layer can have subtle implications on the electrical tunneling behavior of the junctions. We used room-temperature probing of variable junction areas, combined with Ambegaokar-Baratoff physics, to characterize the wafer scale critical current densities. For 0.4 $\mu$m${}^2$ junctions, we found junction spreads as low as 2.0% across the 20 x 20 mm chip relevant for device performance. The entire process was carried out using standard industry foundry processing using 150 mm wafer tooling, which is an important step towards proving that Ta-based junctions can be implemented at scale. We have successfully fabricated and tested junctions with $\alpha$-Ta electrodes and a ${\mathrm{TaO}}_x$ insulating tunnel barrier, demonstrating that this is a material platform which merits further investigation and studies for potential application in classical and quantum superconducting technologies.

arXiv comment26 pages, 12 figures, to be submitted to Physical Review Applied, authors listed alphabetically