Enabling Ultra-Low-Power Always-On Feedforward Leakage Suppression Logic Circuits with FDSOI

Abstract

The growing deployment of real-time applications on wearable and Internet of Things (IoT) edge devices has intensified the need for energy-efficient, high-performance systems that meet stringent timing and energy constraints. Events-driven architectures leverage the sparsity of real-time to further improve system energy efficiency by employing an always-on (AO) domain to monitor inputs and activate a high-performance (HP) domain only when relevant events occur. However, for low-duty-cycle applications, the energy bottleneck shifts toward the AO domain, where leakage power dominates overall consumption. To mitigate this issue, AO circuits are typically implemented using high voltage threshold (HVT) or ultra-high voltage threshold (UHVT) transistors, thereby avoiding sub- and near-threshold operation, which is highly sensitive to process, voltage, and temperature (PVT) variations. In this context, feedforward leakage suppression logic (FLSL) has recently emerged as a promising candidate, offering reduced leakage compared to conventional. However, previous studies report a significant degradation in FLSL leakage performance in technology nodes below 90 nm, primarily due to increased gate and junction leakage currents. FDSOI technology, with its ability to effectively suppress junction leakage, provides an opportunity to overcome this limitation and restore FLSL efficiency in advanced nodes. Therefore, we demonstrate in this work that FLSL implemented in a 22 nm FDSOI technology can significantly reduce the energy consumption of small AO circuits with low-frequency inputs compared to state-of-the-art ultra-low-power CMOS designs. Silicon measurements on an FIR filter and an AES cryptographic core show reduced operating voltage and up to 9.8 x and 1.83 x reductions in leakage power compared to equivalent HVT and UHVT CMOS implementations, respectively.