Bounds and constructions for constant/low-power error-correcting cooling codes

Abstract

The low-power error-correcting cooling (LPECC) codes and constant-power error-correcting cooling (CPECC) codes, introduced in [IEEE Trans. Inf. Theory, 64 (2018), 3062--3085; 66 (2020), 4804--4818], respectively, are two coding schemes designed to simultaneously control the peak temperature and average power consumption of on-chip buses while providing error-correction capability for transmitted information. This paper establishes new upper bounds for both $(n,1,w,w-2)$-CPECC codes and $(n,t,w,w-2)$-CPECC codes using graph-theoretic techniques, and constructs several new families of optimal CPECC codes using combinatorial configurations. Moreover, it completely resolves the conjecture concerning CPECC codes posed in [IEEE Trans. Inf. Theory, DOI: 10.1109/TIT.2026.3721101]. Finally, we derive a new upper bound for $(n,t,w,w-2)$-LPECC codes by probabilistic method, along with new optimal families, and establish the relationship between optimal $(n,t,w,w-2)$-LPECC codes and optimal $(n+1,t,w,w-2)$-CPECC codes.