Design of a Quantum Error Correction Decoder Exploiting Temporal Parallelism
arXiv:2607.27930
The paper presents a microarchitectural design for a quantum error correction decoder that leverages temporal parallelism and the Union-Find algorithm, implemented as an ASIC, achieving about a 35% reduction in decoding latency at code distance 21 while preserving a logical error threshold near 1.5% under phenomenological noise.
Abstract
In the pursuit of fault-tolerant quantum computing, low-latency quantum error correction (QEC) is essential to prevent rapid error accumulation within the syndrome measurement cycle. In this work, we propose a microarchitecture that implements the sandwich decoding method using the Union-Find algorithm by exploiting temporal parallelism, and we present an ASIC implementation. Through logic synthesis and simulation, we show that the proposed decoder achieves an average latency reduction of 35% at code distance d = 21 compared with a conventional batch Union-Find decoder, while maintaining a comparable logical error threshold of approximately 1.5% under phenomenological noise.
11 pages, 11 figures, 2 tables. Accepted at IEEE International Conference on Quantum Computing and Engineering (QCE) 2026