Closed Timelike Curve Decoding on Quantum Hardware
arXiv:2607.27473
The paper presents a finite‑dimensional circuit model for Deutsch closed timelike curves and demonstrates how to implement the associated post‑selected decoder on IBM quantum hardware, evaluating its fidelity and noise characteristics.
Abstract
Deutsch closed timelike curves (D-CTCs) are described by a fixed-point condition for a chronology-violating register. We study a finite-dimensional circuit model that places a Hayden--Preskill/Yoshida--Kitaev recovery map inside such a consistency loop. A register-routing construction makes the Deutsch map explicit: an initial SWAP moves the incoming CTC state to an idle dump register, the scrambler and decoder act on the remaining active registers, and a final SWAP writes the recovered message back to the CTC register. When the active branch recovers the message, the induced map on the CTC register is the replacement channel \(σ\mapsto ρ_M\), with the unique fixed point \(ρ_M\). We implement the associated Lloyd-type post-selected decoder circuits on quantum hardware and formulate a classical-feedback iteration for the experimentally estimated map. Qiskit simulations and IBM-hardware data for single-qubit instances quantify decoder fidelity, post-selection overhead, routing-dependent noise, and quantum-geometric susceptibility.
16 pages, 13 figures