Hierarchical Quantum Logical Processor with Amortized Long-Range Connectivity

Abstract

High qubit overhead is a key bottleneck for fault-tolerant quantum computation. Quantum low-density parity-check (qLDPC) codes offer high encoding efficiency but typically require non-local connectivity in every syndrome extraction cycle, incurring additional physical errors and implementation complexity. We introduce a hierarchical logical processor (HLP) architecture that implements a high-rate quantum CSS code with distance-$d_0$ rotated surface codes (RSC), allowing long-range connectivity to be used only once every $\Theta (d_0)$ rounds of surface-code syndrome extraction. HLPs introduce elongated RSC patches called shuttle buses. Using transversal hybrid-unit CNOT gates, a single shuttle bus can simultaneously couple to multiple standard RSC patches. This capability enables efficient level-1 syndrome extraction with suppressed level-1 error correlations and supports highly parallel logical Pauli measurements. We perform circuit-level simulations of several concrete HLP constructions and benchmark both logical memory and logical Pauli measurement performance. At a physical error rate of $10^{-3}$, a hierarchical logical processor can achieve 3-4 times higher qubit efficiency than the rotated surface code and 20-30 times shorter logical error-correction cycle times than the yoked surface code.

36 pages (7 main + 29 supplemental), 20 figures. Improved presentation