Analysis of Edge Mismatch and Output Power Degradation in Cascoded Class-D Power Amplifiers Using Dual-Range Voltage Level Shifters

Abstract

This paper presents a low-jitter \ac{HVLS} architecture for high-speed mixed-signal and digital power-amplifier applications. The proposed design employs a regenerative cross-coupled feedback network to simultaneously generate two synchronized voltage-domain outputs (e.g., the nominal supply voltage ($V_{\mathrm{DDL}}$) and one at twice its value ($V_{\mathrm{DDH}}=2V_{\mathrm{DDL}}$)). This enables direct drive of cascoded class-D power amplifiers without additional delay-calibration circuitry, amongst other mixed-signal applications. A prototype \ac{HVLS} circuit, together with an impedance-matching network and a pre-driver for high-speed off-chip characterization, was fabricated in a 22-nm FD-SOI process technology. The total die area, including all interface circuitry, is 477$\times$462~$\mu$m${}^2$, while the active area of the \ac{HVLS} core is 3.26$\times$2~$\mu$m${}^2$. Measured at 12.2~GHz, the circuit dissipates 4.43~\textbf{$\mu$W} per switching cycle and achieves an output jitter below 150~fs-rms.

14 pages, 23 figures, 2 Tables