Lightweight Targeted Estimation of Layout Noise in a Quantum Computer using Quality Indicator Circuits

Abstract

Minimizing noise is essential for reliably executing quantum circuits on the current generation of hardware. The mapping of an abstract quantum circuit to the physical layout of the quantum hardware significantly influences the output quality since hardware noise profiles are non-uniform and dynamic. Existing solutions such as Mapomatic relies on stale calibrations while Just-In-Time (JIT) Transpilation has high hardware usage. We propose Quality Indicator Circuits (QICs) as a lightweight probe circuit synthesized from the user circuit, whose ideal noiseless outcome is known. QIC helps decide the region of the quantum hardware best suited for the given circuit. We propose QIC execution for each isomorphic layout, and an alternative approach where a union of multiple layouts are executed together for lower overheads. Our results show QIC to outperform Mapomatic in the quality of layout selection while having 79 percent lower hardware overheads than JIT. This makes our QIC method lightweight, reliable and a viable technique for layout selection in near-term quantum devices.

To appear in Quantum Information Processing (QIP, Springer-Nature)