SR-NCL: an Area-/Energy-Efficient Resilient NCL Architecture Based on Selective Redundancy
arXiv:2506.15634 · doi:10.1109/ISCAS56072.2025.11043864
Abstract
Duplication-based redundancy schemes have proven to be effective in designing fully-resilient Quasi-delay Insensitive (QDI) asynchronous circuits. The complete resiliency, however, is accompanied by significant energy, latency, and area overhead. This paper presents a novel error-tolerant Null Convention Logic (NCL) architecture based on selective redundancy. Results demonstrate the efficacy of the proposed method in terms of area and energy utilization as compared to existing duplication-based NCL designs, targeting an image processing application.
5 pages. Accepted for publication in the Proceedings of IEEE ISCAS 2025