Benchmarking and Validation of Sub-mW 30GHz VG-LNAs in 22nm FDSOI CMOS for 5G/6G Phased-Array Receivers

Abstract

Next-generation (5G/6G) wireless systems demand low-power mm-wave phased-array ICs. Variable-gain LNAs (VGLNAs) are key building blocks enabling hardware complexity reduction, performance enhancement and functionality extension. This paper reports a performance benchmarking of two low-power 30GHz VG-LNAs for phased-array ICs, which provide a 7.5dB gain control for 18dB Taylor taper in a 30GHz 8x8 antenna array, for a comprehensive validation of the new class of VGLNAs and its design methodology. In particular, this paper reports a second and implementation (VG-LNA2) with a reduced number (four) of gain-control back-gate voltages and super-low-Vt MOSFETs, with respect to the previous first implementation (VG-LNA1) with six gain-control back-gate voltages and regular- Vt MOSFETs, both in the same 22nm FDSOI CMOS technology. The results show that VG-LNA2 exhibits performance comparable to those of VG-LNA1, with a slightly lower power consumption. Overall, the performance benchmarking shows that the design methodology adopted for the new class of VG-LNAs leads to record low-power consumption and small form factor solutions reaching the targeted performances, regardless of the arrangements of the back-gate voltages for gain control and transistor sets, resulting in a comprehensive validation of the innovative design features and effective design methodology.

The final version of this draft will be appearing in the Proceedings of DTTIS 2024 available on IEEE Xplore Digital Library