Route-Forcing: Scalable Quantum Circuit Mapping for Scalable Quantum Computing Architectures

Abstract

Quantum computers are expected to scale in size to close the gap that currently exists between quantum algorithms and quantum hardware. To this end, quantum compilation techniques must scale along with the hardware constraints, shifting the current paradigm of obtaining an optimal compilation to relying on heuristics that allow for a fast solution, even though the quality of such a solution may not be optimal. Significant concerns arise as the execution time of current mapping techniques experiences a notable increase when applied to quantum computers with a high number of qubits. In this work, we present Route-Forcing, a quantum circuit mapping algorithm that shows an average speedup of $3.7\times$ compared to the state-of-the-art scalable techniques, reducing the depth of the mapped circuit by $4.7\times$ at the expense of adding $1.3\times$ more SWAP gates. Moreover, the proposed mapping algorithm is adapted and tuned for what is expected to be the next generation of quantum computers, in which different processors are interconnected to increase the total number of qubits, allowing for more complex computations.

arXiv commentAccepted to IEEE QCE 2024

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Cited by in corpus (5)

• An Accurate and Efficient Analytic Model of Fidelity Under Depolarizing Noise Oriented to Large Scale Quantum System Design
• TeleSABRE: Layout Synthesis in Multi-Core Quantum Systems with Teleport Interconnect
• On the Impact of Classical and Quantum Communication Networks Upon Modular Quantum Computing Architecture System Performance
• QSteed: A Resource-Virtualized and Hardware-Aware Quantum Compilation Framework for Real Quantum Computing Processors
• Quantum Circuit Pruning: Improving Fidelity via Compilation-Aware Circuit Approximation