Study of neutron irradiation effects in Depleted CMOS detector structures

Abstract

In this paper results of Edge-TCT and I-V measurements with passive test structures made in LFoundry 150 nm HV-CMOS process on p-type substrates with different initial resistivities ranging from 0.5 to 3 k$\hat{I}\text{c◯}$cm are presented. Samples were irradiated with reactor neutrons up to a fluence of 2$\cdot$10${}^{15}$ n${}_{\mathrm{eq}}$/cm${}^2$. Depletion depth was measured with Edge-TCT. Effective space charge concentration $N_{\mathrm{eff}}$ was estimated from the dependence of depletion depth on bias voltage and studied as a function of neutron fluence. Dependence of $N_{\mathrm{eff}}$ on fluence changes with initial acceptor concentration in agreement with other measurements with p-type silicon. Long term accelerated annealing study of $N_{\mathrm{eff}}$ and detector current up to 1280 minutes at 60${}^{\circ }$C was made. It was found that $N_{\mathrm{eff}}$ and current in reverse biased detector behaves as expected for irradiated silicon.