Scaling Up Silicon Photonic-based Accelerators: Challenges and Opportunities

Abstract

Digital accelerators in the latest generation of CMOS processes support multiply and accumulate (MAC) operations at energy efficiencies spanning 10-to-100~fJ/Op. But the operating speed for such MAC operations are often limited to a few hundreds of MHz. Optical or optoelectronic MAC operations on today's SOI-based silicon photonic integrated circuit platforms can be realized at a speed of tens of GHz, leading to much lower latency and higher throughput. In this paper, we study the energy efficiency of integrated silicon photonic MAC circuits based on Mach-Zehnder modulators and microring resonators. We describe the bounds on energy efficiency and scaling limits for NxN optical networks with today's technology, based on the optical and electrical link budget. We also describe research directions that can overcome the current limitations.

arXiv commentThis article may be downloaded for personal use only. Any other use requires prior permission of the author and AIP Publishing. This article appeared in "M. A. Al-Qadasi, L. Chrostowski, B. J. Shastri, and S. Shekhar , "Scaling up silicon photonic-based accelerators: Challenges and opportunities", APL Photonics 7, 020902 (2022)", and may be found at https://doi.org/10.1063/5.0070992

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