Architectural considerations in the design of a third-generation superconducting quantum annealing processor

Abstract

Early generations of superconducting quantum annealing processors have provided a valuable platform for studying the performance of a scalable quantum computing technology. These studies have directly informed our approach to the design of the next-generation processor. Our design priorities for this generation include an increase in per-qubit connectivity, a problem Hamiltonian energy scale similar to previous generations, reduced Hamiltonian specification errors, and an increase in the processor scale that also leaves programming and readout times fixed or reduced. Here we discuss the specific innovations that resulted in a processor architecture that satisfies these design priorities.

References in corpus (4)

• Observation of topological phenomena in a programmable lattice of 1,800 qubits
• A scalable control system for a superconducting adiabatic quantum optimization processor
• Next-Generation Topology of D-Wave Quantum Processors
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Cited by in corpus (5)

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• Quantum annealing with pairs of ${}^2\Sigma$ molecules as qubits
• Multi-disk clutch optimization using quantum annealing