Performance of Superconducting Quantum Computing Chips under Different Architecture Design
arXiv:2105.06062 · doi:10.1007/s11128-022-03571-0
Abstract
Existing and near-term quantum computers can only perform two-qubit gates between physically connected qubits. Research has been done on compilers to rewrite quantum programs to match hardware constraints. However, the quantum processor architecture, in particular the qubit connectivity and topology, still lacks enough discussion, while it potentially has a huge impact on the performance of the quantum algorithms. We perform a quantitative and comprehensive study on the quantum processor performance under different qubit connectivity and topology. We select ten representative design models with different connectivities and topologies from quantum architecture design space and benchmark their performance by running a set of standard quantum algorithms. It is shown that a high-performance architecture almost always comes with a design with a large connectivity, while the topology shows a weak influence on the performance in our experiment. Different quantum algorithms show different dependence on quantum chip connectivity and topologies. This work provides quantum computing researchers with a systematic approach to evaluating their processor design.
Wei Hu and Yang Yang contributed equally to this work. Corresponding authors: Hua Xu and Xin-Ding Zhang. Submitted to qip
References in corpus (6)
- Supplementary information for "Quantum supremacy using a programmable superconducting processor"
- Surface codes: Towards practical large-scale quantum computation
- Experimental Comparison of Two Quantum Computing Architectures
- Detecting arbitrary quantum errors via stabilizer measurements on a sublattice of the surface code
- Quantum computing with neutral atoms
- Detecting bit-flip errors in a logical qubit using stabilizer measurements