A Survey on Coarse-Grained Reconfigurable Architectures from a Performance Perspective

Abstract

With the end of both Dennard's scaling and Moore's law, computer users and researchers are aggressively exploring alternative forms of computing in order to continue the performance scaling that we have come to enjoy. Among the more salient and practical of the post-Moore alternatives are reconfigurable systems, with Coarse-Grained Reconfigurable Architectures (CGRAs) seemingly capable of striking a balance between performance and programmability. In this paper, we survey the landscape of CGRAs. We summarize nearly three decades of literature on the subject, with a particular focus on the premise behind the different CGRAs and how they have evolved. Next, we compile metrics of available CGRAs and analyze their performance properties in order to understand and discover knowledge gaps and opportunities for future CGRA research specialized towards High-Performance Computing (HPC). We find that there are ample opportunities for future research on CGRAs, in particular with respect to size, functionality, support for parallel programming models, and to evaluate more complex applications.

References in corpus (5)

• Training deep neural networks with low precision multiplications
• Combined Spatial and Temporal Blocking for High-Performance Stencil Computation on FPGAs Using OpenCL
• Automatic Nested Loop Acceleration on FPGAs Using Soft CGRA Overlay
• eBrainII: A 3 kW Realtime Custom 3D DRAM integrated ASIC implementation of a Biologically Plausible Model of a Human Scale Cortex
• Towards an Area-Efficient Implementation of a High ILP EDGE Soft Processor

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• Pipelined Backpropagation at Scale: Training Large Models without Batches
• Reconfigurable Stream Network Architecture
• A flexible framework for early power and timing comparison of time-multiplexed CGRA kernel executions
• Monomorphism-based CGRA Mapping via Space and Time Decoupling
• Towards a Domain Specific Solution for a New Generation of Wireless Modems
• Accelerating PageRank Algorithmic Tasks with a new Programmable Hardware Architecture
• Matrix Engines for High Performance Computing:A Paragon of Performance or Grasping at Straws?