Understanding Quantum Control Processor Capabilities and Limitations through Circuit Characterization

Abstract

Continuing the scaling of quantum computers hinges on building classical control hardware pipelines that are scalable, extensible, and provide real time response. The instruction set architecture (ISA) of the control processor provides functional abstractions that map high-level semantics of quantum programming languages to low-level pulse generation by hardware. In this paper, we provide a methodology to quantitatively assess the effectiveness of the ISA to encode quantum circuits for intermediate-scale quantum devices with O($10^2$) qubits. The characterization model that we define reflects performance, the ability to meet timing constraint implications, scalability for future quantum chips, and other important considerations making them useful guides for future designs. Using our methodology, we propose scalar (QUASAR) and vector (qV) quantum ISAs as extensions and compare them with other ISAs in metrics such as circuit encoding efficiency, the ability to meet real-time gate cycle requirements of quantum chips, and the ability to scale to more qubits.

10 pages, 8 figures

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• HiSEP-Q: A Highly Scalable and Efficient Quantum Control Processor for Superconducting Qubits
• Neural network accelerator for quantum control
• DisQ: A Novel Quantum Output State Classification Method on IBM Quantum Computers using OpenPulse
• State-dependent Routing Dynamics in Noisy Quantum Computing Devices