Hardware-friendly Neural Network Architecture for Neuromorphic Computing

Abstract

The hardware-software co-optimization of neural network architectures is becoming a major stream of research especially due to the emergence of commercial neuromorphic chips such as the IBM Truenorth and Intel Loihi. Development of specific neural network architectures in tandem with the design of the neuromorphic hardware considering the hardware constraints will make a huge impact in the complete system level application. In this paper, we study various neural network architectures and propose one that is hardware-friendly for a neuromorphic hardware with crossbar array of synapses. Considering the hardware constraints, we demonstrate how one may design the neuromorphic hardware so as to maximize classification accuracy in the trained network architecture, while concurrently, we choose a neural network architecture so as to maximize utilization in the neuromorphic cores. We also proposed a framework for mapping a neural network onto a neuromorphic chip named as the Mapping and Debugging (MaD) framework. The MaD framework is designed to be generic in the sense that it is a Python wrapper which in principle can be integrated with any simulator tool for neuromorphic chips.

18 pages, 14 figures, 4 tables, submitted to Frontiers in Neuroscience

References in corpus (4)

• Very Deep Convolutional Networks for Large-Scale Image Recognition
• Training and Operation of an Integrated Neuromorphic Network Based on Metal-Oxide Memristors
• MaD: Mapping and debugging framework for implementing deep neural network onto a neuromorphic chip with crossbar array of synapses
• RRAM based neuromorphic algorithms