Graph Processing on FPGAs: Taxonomy, Survey, Challenges
arXiv:1903.06697
Abstract
Graph processing has become an important part of various areas, such as machine learning, computational sciences, medical applications, social network analysis, and many others. Various graphs, for example web or social networks, may contain up to trillions of edges. The sheer size of such datasets, combined with the irregular nature of graph processing, poses unique challenges for the runtime and the consumed power. Field Programmable Gate Arrays (FPGAs) can be an energy-efficient solution to deliver specialized hardware for graph processing. This is reflected by the recent interest in developing various graph algorithms and graph processing frameworks on FPGAs. To facilitate understanding of this emerging domain, we present the first survey and taxonomy on graph computations on FPGAs. Our survey describes and categorizes existing schemes and explains key ideas. Finally, we discuss research and engineering challenges to outline the future of graph computations on FPGAs.
References in corpus (7)
- GraphLab: A New Framework For Parallel Machine Learning
- Demystifying Parallel and Distributed Deep Learning: An In-Depth Concurrency Analysis
- The GAP Benchmark Suite
- NXgraph: An Efficient Graph Processing System on a Single Machine
- Survey and Taxonomy of Lossless Graph Compression and Space-Efficient Graph Representations
- An Efficient Graph Accelerator with Parallel Data Conflict Management
- An Efficient Dispatcher for Large Scale GraphProcessing on OpenCL-based FPGAs
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- A High-Fidelity Flow Solver for Unstructured Meshes on Field-Programmable Gate Arrays
- Slim Graph: Practical Lossy Graph Compression for Approximate Graph Processing, Storage, and Analytics
- Building Beyond HLS: Graph Analysis and Others
- FAST: FPGA-based Subgraph Matching on Massive Graphs
- Slim Fly: A Cost Effective Low-Diameter Network Topology
- PEFP: Efficient k-hop Constrained s-t Simple Path Enumeration on FPGA
- Active Access: A Mechanism for High-Performance Distributed Data-Centric Computations
- Substream-Centric Maximum Matchings on FPGA