paper

An Energy-Efficient Configurable Lattice Cryptography Processor for the Quantum-Secure Internet of Things

arXiv:1903.04570 · doi:10.1109/ISSCC.2019.8662528

Abstract

This paper presents a configurable lattice cryptography processor which enables quantum-resistant security protocols for IoT. Efficient sampling architectures, coupled with a low-power SHA-3 core, provide two orders of magnitude energy savings over software. A single-port RAM-based NTT architecture is proposed, which provides ~124k-gate area savings. This is the first ASIC implementation which demonstrates multiple lattice-based protocols proposed for NIST post-quantum standardization.

Published in 2019 IEEE International Solid-State Circuits Conference (ISSCC)

An Energy-Efficient Configurable Lattice Cryptography Processor for the Quantum-Secure Internet of Things · wovepaper