FPGA-Based CNN Inference Accelerator Synthesized from Multi-Threaded C Software

Abstract

A deep-learning inference accelerator is synthesized from a C-language software program parallelized with Pthreads. The software implementation uses the well-known producer/consumer model with parallel threads interconnected by FIFO queues. The LegUp high-level synthesis (HLS) tool synthesizes threads into parallel FPGA hardware, translating software parallelism into spatial parallelism. A complete system is generated where convolution, pooling and padding are realized in the synthesized accelerator, with remaining tasks executing on an embedded ARM processor. The accelerator incorporates reduced precision, and a novel approach for zero-weight-skipping in convolution. On a mid-sized Intel Arria 10 SoC FPGA, peak performance on VGG-16 is 138 effective GOPS.

References in corpus (4)

• Very Deep Convolutional Networks for Large-Scale Image Recognition
• FINN: A Framework for Fast, Scalable Binarized Neural Network Inference
• Binarized Neural Networks
• Accelerating Deep Convolutional Networks using low-precision and sparsity

Cited by in corpus (5)

• Synergy: A HW/SW Framework for High Throughput CNNs on Embedded Heterogeneous SoC
• Toolflows for Mapping Convolutional Neural Networks on FPGAs: A Survey and Future Directions
• Digital Neuron: A Hardware Inference Accelerator for Convolutional Deep Neural Networks
• Module-per-Object: a Human-Driven Methodology for C++-based High-Level Synthesis Design
• TMA: Tera-MACs/W Neural Hardware Inference Accelerator with a Multiplier-less Massive Parallel Processor