Accelerating CNN inference on FPGAs: A Survey
arXiv:1806.01683
Abstract
Convolutional Neural Networks (CNNs) are currently adopted to solve an ever greater number of problems, ranging from speech recognition to image classification and segmentation. The large amount of processing required by CNNs calls for dedicated and tailored hardware support methods. Moreover, CNN workloads have a streaming nature, well suited to reconfigurable hardware architectures such as FPGAs. The amount and diversity of research on the subject of CNN FPGA acceleration within the last 3 years demonstrates the tremendous industrial and academic interest. This paper presents a state-of-the-art of CNN inference accelerators over FPGAs. The computational workloads, their parallelism and the involved memory accesses are analyzed. At the level of neurons, optimizations of the convolutional and fully connected layers are explained and the performances of the different methods compared. At the network level, approximate computing and datapath optimization methods are covered and state-of-the-art approaches compared. The methods and tools investigated in this survey represent the recent trends in FPGA CNN inference accelerators and will fuel the future advances on efficient hardware deep learning.
Cloning our HAL submission in ArXiv, Technical Report - Universite Clermont Auvergne, January 2018
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Cited by in corpus (6)
- AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers
- Physical Side-Channel Attacks on Embedded Neural Networks: A Survey
- Near-Precise Parameter Approximation for Multiple Multiplications on A Single DSP Block
- Learning on Hardware: A Tutorial on Neural Network Accelerators and Co-Processors
- Real-time Artificial Intelligence for Accelerator Control: A Study at the Fermilab Booster
- B-DCGAN:Evaluation of Binarized DCGAN for FPGA