A Specification Format and a Verification Method of Fault-Tolerant Quantum Circuits

Abstract

Quantum computations are expressed in general as quantum circuits, which are specified by ordered lists of quantum gates. The resulting specifications are used during the optimisation and execution of the expressed computations. However, the specification format makes it difficult to verify that optimised or executed computations still conform to the initial gate list specifications: showing the computational equivalence between two quantum circuits expressed by different lists of quantum gates is exponentially complex in the worst case. In order to solve this issue, this work presents a derivation of the specification format tailored specifically for fault-tolerant quantum circuits. The circuits are considered a form consisting entirely of single qubit initialisations, CNOT gates and single qubit measurements (ICM form). This format allows, under certain assumptions, to efficiently verify optimised (or implemented) computations. Two verification methods based on checking stabiliser circuit structures are presented.

7 pages, 4 figures

References in corpus (4)

• Surface codes: Towards practical large-scale quantum computation
• Topological fault-tolerance in cluster state quantum computation
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• Lattice Surgery Translation for Quantum Computation

Cited by in corpus (5)

• Equivalence Checking of Sequential Quantum Circuits
• Effective Compression of Quantum Braided Circuits Aided by ZX-Calculus
• Symbolic Verification of Quantum Circuits
• String Diagrams for Defect-Based Surface Code Computing
• QUANTIFY: A framework for resource analysis and design verification of quantum circuits