Protecting quantum memories using coherent parity check codes

Abstract

Coherent parity check (CPC) codes are a new framework for the construction of quantum error correction codes that encode multiple qubits per logical block. CPC codes have a canonical structure involving successive rounds of bit and phase parity checks, supplemented by cross-checks to fix the code distance. In this paper, we provide a detailed introduction to CPC codes using conventional quantum circuit notation. We demonstrate the implementation of a CPC code on real hardware, by designing a [[4,2,2]] detection code for the IBM 5Q superconducting qubit device. Whilst the individual gate-error rates on the IBM device are too high to realise a fault tolerant quantum detection code, our results show that the syndrome information from a full encode-decode cycle of the [[4,2,2]] CPC code can be used to increase the output state fidelity by post-selection. Following this, we generalise CPC codes to other quantum technologies by showing that their structure allows them to be efficiently compiled using any experimentally realistic native two-qubit gate. We introduce a three-stage CPC design process for the construction of hardware-optimised quantum memories. As a proof-of-concept example, we apply our design process to an idealised linear seven-qubit ion trap. In the first stage of the process, we use exhaustive search methods to find a large set of [[7,3,3]] codes that saturate the quantum Hamming bound for seven qubits. We then optimise over the discovered set of codes to meet the hardware and layout demands of the ion trap device. We also discuss how the CPC design process will generalise to larger-scale codes and other qubit technologies.

arXiv comment42 pages including appendices. Open access version now available on Quantum Science and Technology website (follow DOI link below)

References in corpus (30)

• Quantum Computation with Quantum Dots
• Surface codes: Towards practical large-scale quantum computation
• Improved Simulation of Stabilizer Circuits
• A Class of Quantum Error-Correcting Codes Saturating the Quantum Hamming Bound
• Quantum computation with ions in thermal motion
• A Theory of Fault-Tolerant Quantum Computation
• Demonstration of a small programmable quantum computer with atomic qubits
• High-fidelity quantum logic gates using trapped-ion hyperfine qubits
• High-fidelity two-qubit quantum logic gates using trapped calcium-43 ions
• Quantum Error Correction for Beginners
• Large Scale Modular Quantum Computer Architecture with Atomic Memory and Photonic Interconnects
• High-fidelity preparation, gates, memory and readout of a trapped-ion quantum bit
• Surface code quantum computing by lattice surgery
• Experimental Comparison of Two Quantum Computing Architectures
• Active stabilisation, quantum computation and quantum state synthesis
• Interacting Quantum Observables: Categorical Algebra and Diagrammatics
• Quantum LDPC codes with positive rate and minimum distance proportional to n^{1/2}
• Maximum Likelihood, Minimum Effort
• Experimental demonstration of fault-tolerant state preparation with superconducting qubits
• Topological quantum computing with a very noisy network and local error rates approaching one percent
• Ultrahigh Error Threshold for Surface Codes with Biased Noise
• Fast simulation of stabilizer circuits using a graph state representation
• Multi-Element Logic Gates for Trapped-Ion Qubits
• Flag fault-tolerant error correction with arbitrary distance codes
• Constructions and Noise Threshold of Hyperbolic Surface Codes
• Cryogenic setup for trapped ion quantum computing
• Efficient preparation and detection of microwave dressed-state qubits and qutrits with trapped ions
• Tailored codes for small quantum memories
• Short random circuits define good quantum error correcting codes
• Hybrid quantum computing with ancillas

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