Formalization of Fault Trees in Higher-order Logic: A Deep Embedding Approach
arXiv:1608.06392
Abstract
Fault Tree (FT) is a standard failure modeling technique that has been extensively used to predict reliability, availability and safety of many complex engineering systems. In order to facilitate the formal analysis of FT based analyses, a higher-order-logic formalization of FTs has been recently proposed. However, this formalization is quite limited in terms of handling large systems and transformation of FT models into their corresponding Reliability Block Diagram (RBD) structures, i.e., a frequently used transformation in reliability and availability analyses. In order to overcome these limitations, we present a deep embedding based formalization of FTs. In particular, the paper presents a formalization of AND, OR and NOT FT gates, which are in turn used to formalize other commonly used FT gates, i.e., NAND, NOR, XOR, Inhibit, Comparator and majority Voting, and the formal verification of their failure probability expressions. For illustration purposes, we present a formal failure analysis of a communication gateway software for the next generation air traffic management system.
arXiv commentarXiv admin note: text overlap with arXiv:1505.02648
References in corpus (1)
Cited by in corpus (5)
- Reliability Modeling and Analysis of Communication Networks
- Dynamic Fault Trees Analysis using an Integration of Theorem Proving and Model Checking
- On the Formalization of Importance Measures using HOL Theorem Proving
- Formal Verification of Cyber-Physical Systems using Theorem Proving (Invited Paper)
- Formal Probabilistic Analysis of Dynamic Fault Trees in HOL4