Novel Graph Processor Architecture, Prototype System, and Results

Abstract

Graph algorithms are increasingly used in applications that exploit large databases. However, conventional processor architectures are inadequate for handling the throughput and memory requirements of graph computation. Lincoln Laboratory's graph-processor architecture represents a rethinking of parallel architectures for graph problems. Our processor utilizes innovations that include a sparse matrix-based graph instruction set, a cacheless memory system, accelerator-based architecture, a systolic sorter, high-bandwidth multi-dimensional toroidal communication network, and randomized communications. A field-programmable gate array (FPGA) prototype of the new graph processor has been developed with significant performance enhancement over conventional processors in graph computational throughput.

7 pages, 8 figures, IEEE HPEC 2016

References in corpus (3)

• Parallel Sparse Matrix-Matrix Multiplication and Indexing: Implementation and Experiments
• Exploiting Multiple Levels of Parallelism in Sparse Matrix-Matrix Multiplication
• Standards for Graph Algorithm Primitives

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• Mathematics of Digital Hyperspace
• TabulaROSA: Tabular Operating System Architecture for Massively Parallel Heterogeneous Compute Engines