Hybrid Spintronic-CMOS Spiking Neural Network With On-Chip Learning: Devices, Circuits and Systems

Abstract

Over the past decade Spiking Neural Networks (SNN) have emerged as one of the popular architectures to emulate the brain. In SNN, information is temporally encoded and communication between neurons is accomplished by means of spikes. In such networks, spike-timing dependent plasticity mechanisms require the online programming of synapses based on the temporal information of spikes transmitted by spiking neurons. In this work, we propose a spintronic synapse with decoupled spike transmission and programming current paths. The spintronic synapse consists of a ferromagnet-heavy metal heterostructure where programming current through the heavy metal generates spin-orbit torque to modulate the device conductance. Low programming energy and fast programming times demonstrate the efficacy of the proposed device as a nanoelectronic synapse. We perform a simulation study based on an experimentally benchmarked device-simulation framework to demonstrate the interfacing of such spintronic synapses with CMOS neurons and learning circuits operating in transistor sub-threshold region to form a network of spiking neurons that can be utilized for pattern recognition problems.

The article will appear in a future issue of Physical Review Applied

References in corpus (4)

• Spin-Based Neuron Model with Domain Wall Magnets as Synapse
• Spin-Orbit Torque Induced Spike-Timing Dependent Plasticity
• Spin Orbit Torque Based Electronic Neuron
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• On-chip learning for domain wall synapse based Fully Connected Neural Network
• A Nanoscale Room-Temperature Multilayer Skyrmionic Synapse for Deep Spiking Neural Networks
• Composable Probabilistic Inference Networks Using MRAM-based Stochastic Neurons
• Cryogenic Neuromorphic Hardware
• Intrinsic synaptic plasticity of ferroelectric field effect transistors for online learning
• An Inference and Learning Engine for Spiking Neural Networks in Computational RAM (CRAM)