Characterizing a Four-Qubit Planar Lattice for Arbitrary Error Detection

Abstract

Quantum error correction will be a necessary component towards realizing scalable quantum computers with physical qubits. Theoretically, it is possible to perform arbitrarily long computations if the error rate is below a threshold value. The two-dimensional surface code permits relatively high fault-tolerant thresholds at the ~1% level, and only requires a latticed network of qubits with nearest-neighbor interactions. Superconducting qubits have continued to steadily improve in coherence, gate, and readout fidelities, to become a leading candidate for implementation into larger quantum networks. Here we describe characterization experiments and calibration of a system of four superconducting qubits arranged in a planar lattice, amenable to the surface code. Insights into the particular qubit design and comparison between simulated parameters and experimentally determined parameters are given. Single- and two-qubit gate tune-up procedures are described and results for simultaneously benchmarking pairs of two-qubit gates are given. All controls are eventually used for an arbitrary error detection protocol described in separate work [Corcoles et al., Nature Communications, 6, 2015]

9 pages, 3 figures in Proc. SPIE 9500, Quantum Information and Computation XIII, 95001G (May 21, 2015)

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Cited by in corpus (5)

• Circuit Quantum Electrodynamics
• Building logical qubits in a superconducting quantum computing system
• Broadband Filters for Abatement of Spontaneous Emission in Circuit Quantum Electrodynamics
• Optimisation-free Classification and Density Estimation with Quantum Circuits
• Dynamical dimerization phase in Jaynes-Cummings lattices