Robust and Efficient Elimination of Cache and Timing Side Channels

Abstract

Timing and cache side channels provide powerful attacks against many sensitive operations including cryptographic implementations. Existing defenses cannot protect against all classes of such attacks without incurring prohibitive performance overhead. A popular strategy for defending against all classes of these attacks is to modify the implementation so that the timing and cache access patterns of every hardware instruction is independent of the secret inputs. However, this solution is architecture-specific, brittle, and difficult to get right. In this paper, we propose and evaluate a robust low-overhead technique for mitigating timing and cache channels. Our solution requires only minimal source code changes and works across multiple languages/platforms. We report the experimental results of applying our solution to protect several C, C++, and Java programs. Our results demonstrate that our solution successfully eliminates the timing and cache side-channel leaks while incurring significantly lower performance overhead than existing approaches.

15 pages, 10 figures, submitted to NDSS 2016

Cited by in corpus (7)

• Lord of the Ring(s): Side Channel Attacks on the CPU On-Chip Ring Interconnect Are Practical
• Your Processor Leaks Information - and There's Nothing You Can Do About It
• A Survey of Microarchitectural Side-channel Vulnerabilities, Attacks and Defenses in Cryptography
• Eliminating Timing Side-Channel Leaks using Program Repair
• BasicBlocker: ISA Redesign to Make Spectre-Immune CPUs Faster
• Flushgeist: Cache Leaks from Beyond the Flush
• Pacer: Comprehensive Network Side-Channel Mitigation in the Cloud