A Reduced Latency List Decoding Algorithm for Polar Codes
arXiv:1405.4819 · doi:10.1109/SiPS.2014.6986062
Abstract
Long polar codes can achieve the capacity of arbitrary binary-input discrete memoryless channels under a low complexity successive cancelation (SC) decoding algorithm. But for polar codes with short and moderate code length, the decoding performance of the SC decoding algorithm is inferior. The cyclic redundancy check (CRC) aided successive cancelation list (SCL) decoding algorithm has better error performance than the SC decoding algorithm for short or moderate polar codes. However, the CRC aided SCL (CA-SCL) decoding algorithm still suffer from long decoding latency. In this paper, a reduced latency list decoding (RLLD) algorithm for polar codes is proposed. For the proposed RLLD algorithm, all rate-0 nodes and part of rate-1 nodes are decoded instantly without traversing the corresponding subtree. A list maximum-likelihood decoding (LMLD) algorithm is proposed to decode the maximum likelihood (ML) nodes and the remaining rate-1 nodes. Moreover, a simplified LMLD (SLMLD) algorithm is also proposed to reduce the computational complexity of the LMLD algorithm. Suppose a partial parallel list decoder architecture with list size is used, for an (8192, 4096) polar code, the proposed RLLD algorithm can reduce the number of decoding clock cycles and decoding latency by 6.97 and 6.77 times, respectively.
7 pages, accepted by 2014 IEEE International Workshop on Signal Processing Systems (SiPS)
References in corpus (2)
Cited by in corpus (9)
- LLR-based Successive Cancellation List Decoding of Polar Codes
- A Low-Latency List Successive-Cancellation Decoding Implementation for Polar Codes
- A High Throughput List Decoder Architecture for Polar Codes
- Polar Codes and Their Quantum-Domain Counterparts
- Low-latency List Decoding Of Polar Codes With Double Thresholding
- A High-Throughput Architecture of List Successive Cancellation Polar Codes Decoder with Large List Size
- Hardware Decoders for Polar Codes: An Overview
- A multi-mode area-efficient SCL polar decoder
- A hybrid partial sum computation unit architecture for list decoders of polar codes