Multiplierless Approximate 4-point DCT VLSI Architectures for Transform Block Coding

Abstract

Two multiplierless algorithms are proposed for 4x4 approximate-DCT for transform coding in digital video. Computational architectures for 1-D/2-D realisations are implemented using Xilinx FPGA devices. CMOS synthesis at the 45 nm node indicate real-time operation at 1 GHz yielding 4x4 block rates of 125 MHz at less than 120 mW of dynamic power consumption.

5 pages, 1 figure, corrected Figure 1 (published paper in EL is incorrect)

References in corpus (3)

• A DCT Approximation for Image Compression
• DCT-like Transform for Image Compression Requires 14 Additions Only
• An Integer Approximation Method for Discrete Sinusoidal Transforms

Cited by in corpus (4)

• Low-complexity Image and Video Coding Based on an Approximate Discrete Tchebichef Transform
• A Multiplierless Pruned DCT-like Transformation for Image and Video Compression that Requires 10 Additions Only
• A Class of Low-complexity DCT-like Transforms for Image and Video Coding
• A Multiparametric Class of Low-complexity Transforms for Image and Video Coding