The failure risk analysis of digital circuits

Abstract

To analyze the failure risk of asynchronous digital circuits the time-parameter is introduced into the Boolean algebra replacing the arithmetic operations by logical operations. There considered an example of construction of signals passing through the logical elements, using the described below mathematical apparatus.

In this work there was considered the method of failure risk analysis of digital circuits using an analytic representation of signals within the circuit. At that logical operations had to by replaced by arithmetic operations. The transitions from one signal state to another is described by the Heaviside function