3.5k citations
Counting papers with at most 25 authors, so collaboration author lists do not stand in for the people here.
- Nvidia (United Kingdom)GB136 papers
- Lawrence Berkeley National LaboratoryUS32 papers
- Stanford UniversityUS30 papers
- University of California, BerkeleyUS29 papers
- California Institute of TechnologyUS26 papers
- Massachusetts Institute of TechnologyUS25 papers
- Carnegie Mellon UniversityUS24 papers
- University of Illinois Urbana-ChampaignUS24 papers
- University of TorontoCA24 papers
- University of WashingtonUS23 papers
- Harvard UniversityUS19 papers
- Georgia Institute of TechnologyUS17 papers
8 papers · 2 filters
What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study
Saugata Ghose, Abdullah Giray Yağlıkçı, Raghav Gupta +9
Main memory (DRAM) consumes as much as half of the total system power in a computer today, resulting in a growing need to develop new DRAM architectures and systems that consume le…
Exploiting Row-Level Temporal Locality in DRAM to Reduce the Memory Access Latency
Hasan Hassan, Gennady Pekhimenko, Nandita Vijaykumar +4
This paper summarizes the idea of ChargeCache, which was published in HPCA 2016 [51], and examines the work's significance and future potential. DRAM latency continues to be a crit…
SoftMC: Practical DRAM Characterization Using an FPGA-Based Infrastructure
Hasan Hassan, Nandita Vijaykumar, Samira Khan +6
This paper summarizes the SoftMC DRAM characterization infrastructure, which was published in HPCA 2017, and examines the work's significance and future potential. SoftMC (Soft Mem…
LISA: Increasing Internal Connectivity in DRAM for Fast Data Movement and Low Latency
Kevin K. Chang, Prashant J. Nair, Saugata Ghose +3
This paper summarizes the idea of Low-Cost Interlinked Subarrays (LISA), which was published in HPCA 2016, and examines the work's significance and future potential. Contemporary s…
Voltron: Understanding and Exploiting the Voltage-Latency-Reliability Trade-Offs in Modern DRAM Chips to Improve Energy Efficiency
Kevin K. Chang, Abdullah Giray Yaglıkçı, Saugata Ghose +7
This paper summarizes our work on experimental characterization and analysis of reduced-voltage operation in modern DRAM chips, which was published in SIGMETRICS 2017, and examines…
Tiered-Latency DRAM: Enabling Low-Latency Main Memory at Low Cost
Donghyuk Lee, Yoongu Kim, Vivek Seshadri +3
This paper summarizes the idea of Tiered-Latency DRAM (TL-DRAM), which was published in HPCA 2013, and examines the work's significance and future potential. The capacity and cost-…
Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins
Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko +4
This paper summarizes the idea of Adaptive-Latency DRAM (AL-DRAM), which was published in HPCA 2015, and examines the work's significance and future potential. AL-DRAM is a mechani…
Reducing DRAM Refresh Overheads with Refresh-Access Parallelism
K. K. Chang, D. Lee, Z. Chishti +4
This article summarizes the idea of "refresh-access parallelism," which was published in HPCA 2014, and examines the work's significance and future potential. The overarching objec…