Publications (8)
Lithography Hotspot Detection and Mitigation in Nanometer VLSI
Jhih-Rong Gao, Bei Yu, David Z. Pan
With continued feature size scaling, even state of the art semiconductor manufacturing processes will often run into layouts with poor printability and yield. Identifying lithograp…
Self-Aligned Double Patterning Friendly Configuration for Standard Cell Library Considering Placement
Jhih-Rong Gao, Bei Yu, Ru Huang +1
Self-aligned double patterning (SADP) has become a promising technique to push pattern resolution limit to sub-22nm technology node. Although SADP provides good overlay controllabi…
Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting
Bei Yu, Jhih-Rong Gao, David Z. Pan
Triple patterning lithography (TPL) is one of the most promising techniques in the 14nm logic node and beyond. However, traditional LELELE type TPL technology suffers from native c…
E-BLOW: E-Beam Lithography Overlapping aware Stencil Planning for MCC System
Bei Yu, Kun Yuan, Jhih-Rong Gao +1
Electron beam lithography (EBL) is a promising maskless solution for the technology beyond 14nm logic node. To overcome its throughput limitation, industry has proposed character p…
Methodology for standard cell compliance and detailed placement for triple patterning lithography
Bei Yu, Xiaoqing Xu, Jhih-Rong Gao +1
As the feature size of semiconductor process further scales to sub-16nm technology node, triple patterning lithography (TPL) has been regarded one of the most promising lithography…
L-Shape based Layout Fracturing for E-Beam Lithography
Bei Yu, Jhih-Rong Gao, David Z. Pan
Layout fracturing is a fundamental step in mask data preparation and e-beam lithography (EBL) writing. To increase EBL throughput, recently a new L-shape writing strategy is propos…