Publications (83)
ARLArena: A Unified Framework for Stable Agentic Reinforcement Learning
Xiaoxuan Wang, Han Zhang, Haixin Wang +11
Agentic reinforcement learning (ARL) has rapidly gained attention as a promising paradigm for training agents to solve complex, multi-step interactive tasks. Despite encouraging ea…
LIFT: LLM-Based Pragma Insertion for HLS via GNN Supervised Fine-Tuning
Neha Prakriya, Zijian Ding, Yizhou Sun +1
FPGAs are increasingly adopted in datacenter environments for their reconfigurability and energy efficiency. High-Level Synthesis (HLS) tools have eased FPGA programming by raising…
FlexLLM: Composable HLS Library for Flexible Hybrid LLM Accelerator Design
Jiahao Zhang, Zifan He, Nicholas Fraser +3
We present FlexLLM, a composable High-Level Synthesis (HLS) library for rapid development of domain-specific LLM accelerators. FlexLLM exposes key architectural degrees of freedom…
A Unified Framework for Automated Code Transformation and Pragma Insertion
Stéphane Pouget, Louis-Noël Pouchet, Jason Cong
High-level synthesis, source-to-source compilers, and various Design Space Exploration techniques for pragma insertion have significantly improved the Quality of Results of generat…
ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architectures
Yu-Ting Chen, Jason Cong, Zhenman Fang +2
Compared to conventional general-purpose processors, accelerator-rich architectures (ARAs) can provide orders-of-magnitude performance and energy gains and are emerging as one of t…
Compilation for Dynamically Field-Programmable Qubit Arrays with Efficient and Provably Near-Optimal Scheduling
Daniel Bochen Tan, Wan-Hsuan Lin, Jason Cong
Dynamically field-programmable qubit arrays based on neutral atoms feature high fidelity and highly parallel gates for quantum computing. However, it is challenging for compilers t…
Learning to Compare Hardware Designs for High-Level Synthesis
Yunsheng Bai, Atefeh Sohrabizadeh, Zijian Ding +6
High-level synthesis (HLS) is an automated design process that transforms high-level code into hardware designs, enabling the rapid development of hardware accelerators. HLS relies…
Monolithic 3D FPGAs Utilizing Back-End-of-Line Configuration Memories
Faaiq Waqar, Jiahao Zhang, Anni Lu +3
This work presents a novel monolithic 3D (M3D) FPGA architecture that leverages stackable back-end-of-line (BEOL) transistors to implement configuration memory and pass gates, sign…
Quantum State Preparation Circuit Optimization Exploiting Don't Cares
Hanyu Wang, Daniel Bochen Tan, Jason Cong
Quantum state preparation initializes the quantum registers and is essential for running quantum algorithms. Designing state preparation circuits that entangle qubits efficiently w…
HMT: Semantic Hierarchy-Aware Hierarchical Memory Transformer
Maryam Haghifam, Zifan He, Jason Cong +1
Transformer-based LLMs achieve strong results on many language tasks; however, long inputs remain challenging because context windows are finite, and prefill latency and memory gro…
Dynamic-Width Speculative Beam Decoding for Efficient LLM Inference
Zongyue Qin, Zifan He, Neha Prakriya +2
Large language models (LLMs) have shown outstanding performance across numerous real-world tasks. However, the autoregressive nature of these models makes the inference process slo…
Democratizing Domain-Specific Computing
Yuze Chi, Weikang Qiao, Atefeh Sohrabizadeh +2
In the past few years, domain-specific accelerators (DSAs), such as Google's Tensor Processing Units, have shown to offer significant performance and energy efficiency over general…
When HLS Meets FPGA HBM: Benchmarking and Bandwidth Optimization
Young-kyu Choi, Yuze Chi, Jie Wang +2
With the recent release of High Bandwidth Memory (HBM) based FPGA boards, developers can now exploit unprecedented external memory bandwidth. This allows more memory-bounded applic…
Optimized Multi-Token Joint Decoding with Auxiliary Model for LLM Inference
Zongyue Qin, Ziniu Hu, Zifan He +3
Large language models (LLMs) have achieved remarkable success across diverse tasks, yet their inference processes are hindered by substantial time and energy demands due to single-…
Depth-Optimal Addressing of 2D Qubit Array with 1D Controls Based on Exact Binary Matrix Factorization
Daniel Bochen Tan, Shuohao Ping, Jason Cong
Reducing control complexity is essential for achieving large-scale quantum computing. However, reducing control knobs may compromise the ability to independently address each qubit…
SeDeM: Selective Decompression of Hidden-State Memories for Long-Context Question Answering
Maryam Haghifam, Jason Cong, Yizhou Sun
Long-context inference with large language models (LLMs) is costly: self-attention during prefill scales quadratically with sequence length, and the key-value (KV) cache grows with…
Fine Grain 3D Integration for Microarchitecture Design Through Cube Packing Exploration
Yongxiang Liu, Yuchun Ma, Eren Kurshan +2
Most previous 3D IC research focused on stacking traditional 2D silicon layers, so the interconnect reduction is limited to inter-block delays. In this paper, we propose techniques…
Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesis
Zongyue Qin, Yunsheng Bai, Atefeh Sohrabizadeh +4
In recent years, domain-specific accelerators (DSAs) have gained popularity for applications such as deep learning and autonomous driving. To facilitate DSA designs, programmers us…
Revisiting FPGA Acceleration of Molecular Dynamics Simulation with Dynamic Data Flow Behavior in High-Level Synthesis
Jason Cong, Zhenman Fang, Hassan Kianinejad +1
Molecular dynamics (MD) simulation is one of the past decade's most important tools for enabling biology scientists and researchers to explore human health and diseases. However, d…
A Survey on Graph Neural Network Acceleration: Algorithms, Systems, and Customized Hardware
Shichang Zhang, Atefeh Sohrabizadeh, Cheng Wan +7
Graph neural networks (GNNs) are emerging for machine learning research on graph-structured data. GNNs achieve state-of-the-art performance on many tasks, but they face scalability…
ProgSG: Cross-Modality Representation Learning for Programs in Electronic Design Automation
Yunsheng Bai, Atefeh Sohrabizadeh, Zongyue Qin +3
Recent years have witnessed the growing popularity of domain-specific accelerators (DSAs), such as Google's TPUs, for accelerating various applications such as deep learning, searc…
Accelerating Large Language Model Pretraining via LFR Pedagogy: Learn, Focus, and Review
Neha Prakriya, Jui-Nan Yen, Cho-Jui Hsieh +1
Traditional Large Language Model (LLM) pretraining relies on autoregressive language modeling with randomly sampled data from web-scale datasets. Inspired by human learning techniq…
Computed Tomography Image Enhancement using 3D Convolutional Neural Network
Meng Li, Shiwen Shen, Wen Gao +2
Computed tomography (CT) is increasingly being used for cancer screening, such as early detection of lung cancer. However, CT studies have varying pixel spacing due to differences…
RapidStream IR: Infrastructure for FPGA High-Level Physical Synthesis
Jason Lau, Yuanlong Xiao, Yutong Xie +7
The increasing complexity of large-scale FPGA accelerators poses significant challenges in achieving high performance while maintaining design productivity. High-level synthesis (H…
TENET: A Framework for Modeling Tensor Dataflow Based on Relation-centric Notation
Liqiang Lu, Naiqing Guan, Yuyue Wang +5
Accelerating tensor applications on spatial architectures provides high performance and energy-efficiency, but requires accurate performance models for evaluating various dataflow…
Routing-Aware Placement for Zoned Neutral Atom-based Quantum Computing
Yannick Stade, Wan-Hsuan Lin, Jason Cong +1
Quantum computing promises to solve previously intractable problems, with neutral atoms emerging as a promising technology. Zoned neutral atom architectures allow for immense paral…
Holistic Optimization Framework for FPGA Accelerators
Stéphane Pouget, Michael Lo, Louis-Noël Pouchet +1
Customized accelerators have revolutionized modern computing by delivering substantial gains in energy efficiency and performance through hardware specialization. Field-Programmabl…
AutoAccel: Automated Accelerator Generation and Optimization with Composable, Parallel and Pipeline Architecture
Jason Cong, Peng Wei, Cody Hao Yu +1
CPU-FPGA heterogeneous architectures are attracting ever-increasing attention in an attempt to advance computational capabilities and energy efficiency in today's datacenters. Thes…
Reconfigurable Stream Network Architecture
Chengyue Wang, Xiaofan Zhang, Jason Cong +1
As AI systems grow increasingly specialized and complex, managing hardware heterogeneity becomes a pressing challenge. How can we efficiently coordinate and synchronize heterogeneo…
Optimality Study of Existing Quantum Computing Layout Synthesis Tools
Bochen Tan, Jason Cong
Layout synthesis, an important step in quantum computing, processes quantum circuits to satisfy device layout constraints. In this paper, we construct QUEKO benchmarks for this pro…
Compiling Quantum Circuits for Dynamically Field-Programmable Neutral Atoms Array Processors
Daniel Bochen Tan, Dolev Bluvstein, Mikhail D. Lukin +1
Dynamically field-programmable qubit arrays (DPQA) have recently emerged as a promising platform for quantum information processing. In DPQA, atomic qubits are selectively loaded i…
AI+HW 2035: Shaping the Next Decade
Deming Chen, Jason Cong, Azalia Mirhoseini +27
Artificial intelligence (AI) and hardware (HW) are advancing at unprecedented rates, yet their trajectories have become inseparably intertwined. The global research community lacks…
ML-QLS: Multilevel Quantum Layout Synthesis
Wan-Hsuan Lin, Jason Cong
Quantum Layout Synthesis (QLS) plays a crucial role in optimizing quantum circuit execution on physical quantum devices. As we enter the era where quantum computers have hundreds o…
LUT-LLM: Efficient Large Language Model Inference with Memory-based Computations on FPGAs
Zifan He, Shengyu Ye, Rui Ma +2
The rapid development of large language models (LLM) has greatly enhanced everyday applications. While many FPGA-based accelerators, with flexibility for fine-grained data control,…
Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver
Linghao Song, Licheng Guo, Suhail Basalama +3
The continued growth in the processing power of FPGAs coupled with high bandwidth memories (HBM), makes systems like the Xilinx U280 credible platforms for linear solvers which oft…
Hierarchical Mixture of Experts: Generalizable Learning for High-Level Synthesis
Weikai Li, Ding Wang, Zijian Ding +4
High-level synthesis (HLS) is a widely used tool in designing Field Programmable Gate Array (FPGA). HLS enables FPGA design with software programming languages by compiling the sou…
AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators
Atefeh Sohrabizadeh, Cody Hao Yu, Min Gao +1
Adopting FPGA as an accelerator in datacenters is becoming mainstream for customized computing, but the fact that FPGAs are hard to program creates a steep learning curve for softw…
AgRefactor: Self-Evolving Agentic Workflow for HLS Compatibility and Performance
Yang Zou, Zijian Ding, Yizhou Sun +1
High-Level Synthesis (HLS) provides a fast path from concepts to silicon, but converting real-world software into synthesizable HLS code remains challenging due to restrictive lang…
TAPA: A Scalable Task-Parallel Dataflow Programming Framework for Modern FPGAs with Co-Optimization of HLS and Physical Design
Licheng Guo, Yuze Chi, Jason Lau +9
In this paper, we propose TAPA, an end-to-end framework that compiles a C++ task-parallel dataflow program into a high-frequency FPGA accelerator. Compared to existing solutions, T…
Optimal Qubit Mapping with Simultaneous Gate Absorption
Bochen Tan, Jason Cong
Before quantum error correction (QEC) is achieved, quantum computers focus on noisy intermediate-scale quantum (NISQ) applications. Compared to the well-known quantum algorithms re…
Strategic Plan for Neutral Atom Quantum Computation
Adrian J. Menssen, Tout Wang, Michael Gullans +54
We present a strategic plan for neutral atom quantum computation, bringing together hardware development and theory advancements to achieve the goal of practical quantum advantage.…
Efficient Task Transfer for HLS DSE
Zijian Ding, Atefeh Sohrabizadeh, Weikai Li +3
There have been several recent works proposed to utilize model-based optimization methods to improve the productivity of using high-level synthesis (HLS) to design domain-specific…
Optimal Layout Synthesis for Quantum Computing
Bochen Tan, Jason Cong
Recent years have witnessed the fast development of quantum computing. Researchers around the world are eager to run larger and larger quantum algorithms that promise speedups impo…
MediQ-GAN: Quantum-Inspired GAN for High Resolution Medical Image Generation
Qingyue Jiao, Yongcan Tang, Jun Zhuang +2
Machine learning-assisted diagnosis shows promise, yet medical imaging datasets are often scarce, imbalanced, and constrained by privacy, making data augmentation essential. Classi…
HarnessBridge: Learnable Bidirectional Controller for LLM Agent Harness
Xiaoxuan Wang, Haixin Wang, Alexander Taylor +3
Large language models are increasingly deployed as agents for long-horizon tasks, yet their performance is shaped not only by model capability and environment design, but also by t…
Iceberg: Enhancing HLS Modeling with Synthetic Data
Zijian Ding, Tung Nguyen, Weikai Li +3
Deep learning-based prediction models for High-Level Synthesis (HLS) of hardware designs often struggle to generalize. In this paper, we study how to close the generalizability gap…
Atomique: A Quantum Compiler for Reconfigurable Neutral Atom Arrays
Hanrui Wang, Pengyu Liu, Daniel Bochen Tan +6
The neutral atom array has gained prominence in quantum computing for its scalability and operation fidelity. Previous works focus on fixed atom arrays (FAAs) that require extensiv…
Quantum State Preparation Using an Exact CNOT Synthesis Formulation
Hanyu Wang, Bochen Tan, Jason Cong +1
Minimizing the use of CNOT gates in quantum state preparation is a crucial step in quantum compilation, as they introduce coupling constraints and more noise than single-qubit gate…
Computer Science Challenges in Quantum Computing: Early Fault-Tolerance and Beyond
Jens Palsberg, Jason Cong, Yufei Ding +7
Quantum computing is entering a period in which progress will be shaped as much by advances in computer science as by improvements in hardware. The central thesis of this report is…
Serpens: A High Bandwidth Memory Based Accelerator for General-Purpose Sparse Matrix-Vector Multiplication
Linghao Song, Yuze Chi, Licheng Guo +1
Sparse matrix-vector multiplication (SpMV) multiplies a sparse matrix with a dense vector. SpMV plays a crucial role in many applications, from graph analytics to deep learning. Th…
Logical Resource Estimation for Quantum State Preparation with Compilation
Diyi Liu, Hanyu Wang, Shuchen Zhu +6
Quantum state preparation is a fundamental primitive in quantum algorithms for encoding classical data into quantum amplitudes. We compare the cost of preparing general -qubit s…
HMT: Hierarchical Memory Transformer for Efficient Long Context Language Processing
Zifan He, Yingqi Cao, Zongyue Qin +3
Transformer-based large language models (LLM) have been widely used in language processing applications. However, due to the memory constraints of the devices, most of them restric…
Rapid Cycle-Accurate Simulator for High-Level Synthesis
Yuze Chi, Young-kyu Choi, Jason Cong +1
A large semantic gap between the high-level synthesis (HLS) design and the low-level (on-board or RTL) simulation environment often creates a barrier for those who are not FPGA exp…
Assessing Quantum Layout Synthesis Tools via Known Optimal-SWAP Cost Benchmarks
Shuohao Ping, Wan-Hsuan Lin, Daniel Bochen Tan +1
Quantum layout synthesis (QLS) is a critical step in quantum program compilation for superconducting quantum computers, involving the insertion of SWAP gates to satisfy hardware co…
Can Asymmetric Tile Buffering Be Beneficial?
Chengyue Wang, Wesley Pang, Xinrui Wu +9
General matrix multiplication (GEMM) is the computational backbone of modern AI workloads, and its efficiency is critically dependent on effective tiling strategies. Conventional a…
TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-based FPGAs
Weikang Qiao, Licheng Guo, Zhenman Fang +2
The emergence of high-bandwidth memory (HBM) brings new opportunities to boost the performance of sorting acceleration on FPGAs, which was conventionally bounded by the available o…
Understand and Accelerate Memory Processing Pipeline for Large Language Model Inference
Zifan He, Rui Ma, Yizhou Sun +1
Modern large language models (LLMs) increasingly depends on efficient long-context processing and generation mechanisms, including sparse attention, retrieval-augmented generation…
Stream-HLS: Towards Automatic Dataflow Acceleration
Suhail Basalama, Jason Cong
High-level synthesis (HLS) has enabled the rapid development of custom hardware circuits for many software applications. However, developing high-performance hardware circuits usin…
TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs
Neha Prakriya, Yuze Chi, Suhail Basalama +2
Despite the increasing adoption of Field-Programmable Gate Arrays (FPGAs) in compute clouds, there remains a significant gap in programming tools and abstractions which can leverag…
Enabling Automated FPGA Accelerator Optimization Using Graph Neural Networks
Atefeh Sohrabizadeh, Yunsheng Bai, Yizhou Sun +1
High-level synthesis (HLS) has freed the computer architects from developing their designs in a very low-level language and needing to exactly specify how the data should be transf…
Report for NSF Workshop on AI for Electronic Design Automation
Deming Chen, Vijay Ganesh, Weikai Li +7
This report distills the discussions and recommendations from the NSF Workshop on AI for Electronic Design Automation (EDA), held on December 10, 2024 in Vancouver alongside NeurIP…
SegFold: Accelerating Sparse GEMM with a Fine-Grained Dynamic Dataflow
Xinrui Wu, Hanyu Wang, Jason Cong +1
Generalized sparse matrix-matrix multiplication (SpGEMM) is critical in many domains. Existing CPUs and GPUs, as well as specialized accelerators, rely on static dataflows (e.g., i…
Extending High-Level Synthesis for Task-Parallel Programs
Yuze Chi, Licheng Guo, Jason Lau +3
C/C++/OpenCL-based high-level synthesis (HLS) becomes more and more popular for field-programmable gate array (FPGA) accelerators in many application domains in recent years, thank…
Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach
Stéphane Pouget, Louis-Noël Pouchet, Jason Cong
High-Level Synthesis enables the rapid prototyping of hardware accelerators, by combining a high-level description of the functional behavior of a kernel with a set of micro-archit…
CHARM: Composing Heterogeneous Accelerators for Matrix Multiply on Versal ACAP Architecture
Jinming Zhuang, Jason Lau, Hanchen Ye +10
Dense matrix multiply (MM) serves as one of the most heavily used kernels in deep learning applications. To cope with the high computation demands of these applications, heterogene…
Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition
Saranyu Chattopadhyay, Florian Lonsing, Luca Piccolboni +12
Hardware accelerators (HAs) are essential building blocks for fast and energy-efficient computing systems. Accelerator Quick Error Detection (A-QED) is a recent formal technique wh…
Demystifying FPGA Hard NoC Performance
Sihao Liu, Jake Ke, Tony Nowatzki +1
With the advent of modern multi-chiplet FPGA architectures, vendors have begun integrating hardened NoC to address the scalability, resource usage, and frequency disadvantages of s…
Best-Effort FPGA Programming: A Few Steps Can Go a Long Way
Jason Cong, Zhenman Fang, Yuchen Hao +4
FPGA-based heterogeneous architectures provide programmers with the ability to customize their hardware accelerators for flexible acceleration of many workloads. Nonetheless, such…
SPA-GCN: Efficient and Flexible GCN Accelerator with an Application for Graph Similarity Computation
Atefeh Sohrabizadeh, Yuze Chi, Jason Cong
While there have been many studies on hardware acceleration for deep learning on images, there has been a rather limited focus on accelerating deep learning applications involving…
InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs
Zifan He, Anderson Truong, Yingqi Cao +1
The rise of deep neural networks (DNNs) has driven an increased demand for computing power and memory. Modern DNNs exhibit high data volume variation (HDV) across tasks, which pose…
Search for Optimal Systolic Arrays: A Comprehensive Automated Exploration Framework and Lessons Learned
Jie Wang, Jason Cong
Systolic arrays have been widely used for accelerating HPC and deep learning applications. There is a plethora of previous works on the performance tuning of systolic arrays, but u…
LLM-DSE: Searching Accelerator Parameters with LLM Agents
Hanyu Wang, Xinrui Wu, Zijian Ding +6
Even though high-level synthesis (HLS) tools mitigate the challenges of programming domain-specific accelerators (DSAs) by raising the abstraction level, optimizing hardware direct…
Reuse-Aware Compilation for Zoned Quantum Architectures Based on Neutral Atoms
Wan-Hsuan Lin, Daniel Bochen Tan, Jason Cong
Quantum computing architectures based on neutral atoms offer large scales and high-fidelity operations. They can be heterogeneous, with different zones for storage, entangling oper…
A High-Performance Multilevel Framework for Quantum Layout Synthesis
Shuohao Ping, Naren Sathishkumar, Wan-Hsuan Lin +2
Quantum Layout Synthesis (QLS) is a critical compilation stage that adapts quantum circuits to hardware constraints with an objective of minimizing the SWAP overhead. While heurist…
FIFOAdvisor: A DSE Framework for Automated FIFO Sizing of High-Level Synthesis Designs
Stefan Abi-Karam, Rishov Sarkar, Suhail Basalama +2
Dataflow hardware designs enable efficient FPGA implementations via high-level synthesis (HLS), but correctly sizing first-in-first-out (FIFO) channel buffers remains challenging.…
Pyxis: An Open-Source Performance Dataset of Sparse Accelerators
Linghao Song, Yuze Chi, Jason Cong
Specialized accelerators provide gains of performance and efficiency in specific domains of applications. Sparse data structures or/and representations exist in a wide range of app…
Domain-Specific Quantum Architecture Optimization
Wan-Hsuan Lin, Bochen Tan, Murphy Yuezhen Niu +2
With the steady progress in quantum computing over recent years, roadmaps for upscaling quantum processors have relied heavily on the targeted qubit architectures. So far, similarl…
Quantum Circuit Synthesis Using an Exact T Library
Hanyu Wang, Mingfei Yu, Xinrui Wu +1
In fault-tolerant quantum circuit synthesis, T gates supplied via magic states dominate space-time cost, while Clifford gates incur negligible overhead. Conventional flows minimize…
Q-Pilot: Field Programmable Qubit Array Compilation with Flying Ancillas
Hanrui Wang, Daniel Bochen Tan, Pengyu Liu +4
Neutral atom arrays have become a promising platform for quantum computing, especially the field programmable qubit array (FPQA) endowed with the unique capability of atom movement…
Compilation of QCrank Encoding Algorithm for a Dynamically Programmable Qubit Array Processor
Jan Balewski, Wan-Hsuan Lin, Anupam Mitra +5
Algorithm and hardware-aware compilation co-design is essential for the efficient deployment of near-term quantum programs. We present a compilation case-study implementing QCrank…
FPGA-Based In-Vivo Calcium Image Decoding for Closed-Loop Feedback Applications
Zhe Chen, Garrett J. Blair, Chengdi Cao +5
Miniaturized calcium imaging is an emerging neural recording technique that has been widely used for monitoring neural activity on a large scale at a specific brain region of rats…
Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication
Linghao Song, Yuze Chi, Atefeh Sohrabizadeh +3
Sparse-Matrix Dense-Matrix multiplication (SpMM) is the key operator for a wide range of applications, including scientific computing, graph processing, and deep learning. Architec…
Locality and Utilization in Placement Suboptimality
Jason Cong, Michalis Romesis, Joseph R. Shinnerl +2
The mixed-size placement benchmarks described in this book chapter directly address several of the shortcomings in previously published suboptimality benchmarks. Two new sets of pl…